Presentation: "Lock-free Algorithms for Ultimate Performance. MOVED TO BALLROOM A"
Track:
Mechanical Sympathy
Time: Friday 13:30 - 14:20
Location: Grand Ballroom A
Abstract: "In the challenge to reach the lowest latencies and highest throughputs, the good old fashioned lock imposes too much contention on our algorithms. This contention results in unpredictable latencies when we context switch into the kernel, and in addition limits throughput as Little’s law kicks in. Lock-free and wait-free algorithms can come to the rescue by side-stepping the issues with locks, and when done well can even avoid contention all together. However, lock-free techniques are not for the faint hearted. Programming with locks is hard. Programming using lock-free techniques is often considered the realm occupied only by technical wizards.
This session aims to take some of the fear out of lock-free techniques. Make no mistake this is not a subject for beginners but if you are brave, and enjoy understanding how memory and processors really work, then this session could open your eyes with what is possible if you are willing to dedicate the time and effort in this amazing subject area.
The attendees will learn the basics of how modern Intel x86_64 processors work and the memory model they implement that forms the foundations for lock-free programming. Empirical evidence will be presented to illustrate the raw throughput and potential latencies that can be achieved when using these techniques"
This session aims to take some of the fear out of lock-free techniques. Make no mistake this is not a subject for beginners but if you are brave, and enjoy understanding how memory and processors really work, then this session could open your eyes with what is possible if you are willing to dedicate the time and effort in this amazing subject area.
The attendees will learn the basics of how modern Intel x86_64 processors work and the memory model they implement that forms the foundations for lock-free programming. Empirical evidence will be presented to illustrate the raw throughput and potential latencies that can be achieved when using these techniques"