You are viewing content from a past/completed QCon -

Presentation: Programming the Network Data Plane

Track: Modern CS in the Real World

Location: Pacific DEKJ

Day of week:

Slides: Download Slides

Level: Advanced

Persona: Architect, Backend Developer, Developer


We all know how to program CPUs, making it easy to prototype new ideas, build new applications, and share them with others. Today it is commonplace to program not just CPUs, but almost any domain-specific processors, such as GPUs, DSPs, and even machine-learning accelerators (e.g., TPUs). Unfortunately networking has long been an exception to this trend; the network data plane -- packet processing -- has been dictated by fixed-function switching chips, which help up innovations in the fields of networking, computing, and storage all together.

But this is changing quickly. The new PISA (Protocol-Independent Switch Architecture) ASICs promise multi Tb/s of packet processing with uncompromised programmability. P4, a new domain-specific high-level language designed for networking, additionally allows network engineers and developers to program PISA chips and other types of programmable packet-processing devices (e.g., FPGAs, NPUs, and S/W switches) in a declarative and intuitive fashion. PISA and P4 will entirely change the way people design, build, and run not just their networks, but their distributed systems and applications as well.

In this talk, I’ll first explain what PISA and P4 are, how they work, what kinds of design principles they are built on, and why they are made possible now. I’ll also introduce a few killer applications of these technologies. Then I’ll characterize PISA as a “relentless I/O-event execution machine” and show how this characterization opens up possibilities for joint-engineering a network and the distributed applications running on the network. I’ll conclude my talk by introducing a few such exciting examples.

Speaker: Changhoon Kim

Director of System Architecture @Barefoot Networks

Chang Kim is a Director of System Architecture at Barefoot Networks and is also working actively for the P4 Language Consortium ( Before getting involved with and Barefoot, he worked at Windows Azure, Microsoft’s cloud-service division, and led engineering and research projects on the architecture, performance, and management of datacenter networks. Chang is interested in programmable networking technologies, network monitoring and diagnostics, network verification, self-configuring/running networks, and debugging and diagnosis of large-scale distributed systems. Many of his research contributions — including TPP, VL2, Seawall, EyeQ, Ananta, and SEATTLE — are adopted in large production systems. He received a few awards, including SIGCOMM 2017 Best Paper Award and Microsoft RockStar Award 2013.

Find Changhoon Kim at