Presentation: "Going Under the Hood with Intel?s Next Generation Microarchitecture Codename Haswell"

Time: Friday 16:00 - 16:50

Location: Seacliff CD

Performance matters and how we improve it has been evolving. Historically, transparent hardware improvements would mean software just ran faster. And modern processors already take extensive advantage of parallelism across instructions. However, to continue the pace of innovation, software will need to be increasingly involved in taking advantage of hardware capabilities and the future will need to be increasingly parallel involving parallelism not just across instructions but across data, threads, cores, and nodes.

In this talk, we first take a close look at Intel’s Next Generation Microarchitecture Codename Haswell and discuss how developers can take advantage of its instruction set extensions to achieve higher performance, with an in-depth focus on the Intel® Transactional Synchronization Extensions. We then discuss challenges in how to measure time in such high performance processors and try to clear some myths.

Ravi Rajwar, Intel

 Ravi  Rajwar

Ravi Rajwar is a Microprocessor Architect in the Intel Architecture Development Group currently working on the development of future Intel processors. Most recently he was an architect on the next generation Intel® microarchitecture code named Haswell. He received his M.S. and Ph.D. degrees in Computer Sciences from the University of Wisconsin-Madison.